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MC100EPT622 3.3V LVTTL/LVCMOS to LVPECL Translator
The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The device has an OR- ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs (ENTTL). If the inputs are left open, they will default to the enable state. The device design has been optimized for low channel- to- channel skew
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* * * * * * *
450 ps Typical Propagation Delay Maximum Frequency > 1.5 GHz Typical PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V PNP LVTTL Inputs for Minimal Loading Q Output Will Default HIGH with Inputs Open The 100 Series Contains Temperature Compensation.
ENPECL ENTTL D0 Q0 A WL YY WW LQFP-32 FA SUFFIX CASE 873A 32 1 = Assembly Location = Wafer Lot = Year = Work Week MC100 EPT622 AWLYYWW
D1
*For additional information, see Application Note AND8002/D Q1
D2
Q2
ORDERING INFORMATION
Device Package LQFP32 Shipping 250 Unit Trays 2000 Tape & Reel MC100EPT622FA
D3
Q3
MC100EPT622FAR2 LQFP32
LVCMOS/TTL
D4
Q4 LVPECL
D5
Q5
TRUTH TABLE
ENPECL ENTTL X X H H L D H L H L X Q H L H L L
D6
H Q6 H X Q7 X L
D7
D8
Q8
D9
Q9
Figure 1. Logic Symbol
(c) Semiconductor Components Industries, LLC, 2002
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December, 2002 - Rev. 2
Publication Order Number: MC100EPT622/D
MC100EPT622
VCCO VCCO VCCO
Q0
Q1
Q2
Q3
Q4
PIN DESCRIPTION
24 VCCO D0 D1 VEE D2 D3 D4 VCCO 25 26 27 28 23 22 21 20 19 18 17 16 15 14 13 VCCO Q5 Q6 VCC Q7 Q8 Q9 VCCO PIN D0:9 Q0:9 ENTTL ENPECL VCC VEE FUNCTION Data Input (TTL) Data Output (PECL) Enable Control (TTL) Enable Control (PECL) Positive Supply Ground
MC100EPT622
29 30 31 32 1 2 3 4 5 6 7 8 12 11 10 9
ENTTL
ENPECL
D7
D8
D9
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View) ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value N/A N/A > 2 kV > 150 V > 2 kV Level 2 UL 94 V-0 @ 0.125 in 596 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Oxygen Index: 28 to 34
MAXIMUM RATINGS (Note 1)
Symbol VCC VI Iout TA Tstg qJA qJC Tsol Power Supply Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 32 LQFP 32 LQFP 32 LQFP Parameter Condition 1 VEE = 0 V VEE = 0 V Continuous Surge VI VCC Condition 2 Rating 5 5 to 0 50 100 -40 to +85 -65 to +150 80 55 12 to 17 265 Units V V mA mA C C C/W C/W C/W C
1. Maximum Ratings are those values beyond which device damage may occur.
VEE
D5
D6
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MC100EPT622
TTL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = -40C to 85C
Symbol IIH IIHH IIL VIK VIH VIL Characteristic Input HIGH Current Input HIGH Current MAX Input LOW Current Input Clamp Voltage Input HIGH Voltage Input LOW Voltage Condition VIN= 2.7 V VIN= VCC VIN= 0.5 V IIN= -18 mA -1.2 2.0 0.8 -0.9 Min Typ Max 25 100 -0.6 Unit mA mA mA V V V
PECL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = -40C to 85C
Symbol IIH IIL VIH VIL Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage Condition VIN= 2420 mV VIN= 1490 mV 2075 1490 Min Typ Max 150 200 2420 1675 Unit mA mA mV mV
PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 2)
-40 C Symbol IEE VOH VOL Characteristic Power Supply Current Input High Voltage (Note 3) Input Low Current (Note 3) Min 85 2155 1355 Typ 115 2280 1520 Max 145 2405 1700 Min 90 2155 1355 25C Typ 120 2280 1520 Max 155 2405 1700 Min 95 2155 1355 85C Typ 130 2280 1520 Max 155 2405 1700 Unit mA mV mV
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 2. Input and output parameters vary 1:1 with VCC. 3. All loading with 50 W to VCC- 2.0 V.
AC CHARACTERISTICS VCC = 3.0 V to 3.8 V (Note 4)
-40 C Symbol fmax tPLH, tPHL Characteristic Maximum Frequency (See Figure 2) Propagation Delay to Output (Figure 3, Note 5) D to Q ENPECL to Q ENTTL to Q Random Clock Jitter (RMS) (See Figure 2) Output Rise/Fall Times (20% - 80%) Duty Cycle Skew (Note 6) D to Q ENPECL to Q ENTTL to Q Channel 0-7 Channel 8-9 100 Min 1.0 Typ 1.5 Max Min 1.0 25C Typ 1.5 Max Min 1.0 85C Typ 1.5 Max Unit GHz ps 100 150 300 450 500 450 0.7 200 800 875 800 3.0 450 100 100 150 300 500 500 500 0.7 200 875 875 800 3.0 250 100 100 200 300 500 550 500 0.7 200 800 925 800 3.0 300 ps ps ps 120 200 120 100 375 775 400 275 120 200 120 100 375 775 400 275 120 200 120 100 375 775 400 275
tJITTER tr / tf TSKEW
4. Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V. 5. 1.5 V to 50% point of the output. 6. Duty cycle skew |tPLH - tPHL| on the specific path.
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MC100EPT622
2400 2200 OUTPUT AMPLITUDE (mV) 2000 1800 1600 1400 RMS Jitter (ps) 1200 1000 0.5 VCC = 3.3 V TA = 25C VOH (mV) VOL (mV) 10.0 9.0 8.0 RMS JITTER (ps) 7.0 6.0 5.0 4.0 3.0 2.0 1.0 1.0 1.5 2.0 0.0
FREQUENCY (GHz)
Figure 2. Average Output Amplitude/Jitter (3.3 V, 255C)
800
600 tPLH, tPHL (ps) 500 400 300 200 100 0
Figure 3. Average Propagation Delay (3.3 V, 255C)
Driver Device 50 W
Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
EE E EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EE EE
tPHL CHANNEL Q D Receiver Device VTT VTT = VCC - 2.0 V
700
tPLH
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MC100EPT622
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020 ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS PlusTM Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC100EPT622
PACKAGE DIMENSIONS
LQFP FA SUFFIX 32-LEAD PLASTIC PACKAGE CASE 873A-02 ISSUE A
A
32
4X 25
A1
0.20 (0.008) AB T-U Z
1
-TB B1
8
-UV P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z9 S1 S
4X
0.20 (0.008) AC T-U Z
G -ABSEATING PLANE
DETAIL AD
-ACBASE METAL
N
F
8X
D
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 _ REF 12 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 _ REF 12 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
CE
SECTION AE-AE
X DETAIL AD
GAUGE PLANE
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0.250 (0.010)
H
W
K
Q_
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z-
EE EE EE
MC100EPT622
Notes
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MC100EPT622
ECLinPS Plus is a trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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MC100EPT622/D

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